The present invention relates to a semiconductor device having a lightly doped drain (LDD) region (low concentration diffusion region) and a method for manufacturing the same.
In recent years, the demand for high integration of semiconductor devices has increased greatly. Under these conditions, there has been an increasing demand for forming a plurality of transistors having different voltage capacity characteristics on the same semiconductor substrate. The formation of the plurality of transistors having different voltage capacities on the same semiconductor substrate enables adjustment of the gate length or the concentration of implanted impurity to the source region and drain region for each transistor.
When forming transistors by such adjustment, the device size tends to increase. For example, when low concentration impurity is implanted to the semiconductor substrate to form an LDD region for a transistor having normal voltage capacity after forming a transistor having a higher voltage capacity, the impurity may also be implanted into the drain region and source region of the high voltage transistor. The implanting of the impurity into the drain region and source region of the high voltage transistor tends to decrease the junction voltage capacity between the impurity implanted in the high voltage transistor and the well in which the high voltage resistant transistor is formed. In such a case, the gate length must be set longer so as to impart the desired voltage capacity characteristics to the high voltage transistor.
When transistors having various voltage capacities characteristics are formed on the same semiconductor substrate in this way, it becomes difficult to satisfy the requirement for miniaturization of the semiconductor device since the device size of the high voltage transistor tends to increase.
It has been proposed in the prior art, for example, as described in Japanese Patent No. 3125752, to form a high voltage transistor using shallow trench isolation (STI) technology by forming trenches under opposite sides of a gate and implanting insulation material in the trenches so as to form a source region and a drain region. By forming the high voltage transistor in this manner, the insulation material that fills the trenches functions as a mask. Thus, it is possible, when forming the LDD region of a transistor having normal voltage capacity, to avoid implanting impurity into the well in which the high voltage transistor is formed. Accordingly, the gate length of the high voltage transistor may be reduced, and the semiconductor device may be miniaturized.
The high voltage transistor of Japanese Patent No. 3125752 requires the impurity concentration of the source region and drain region to be decreased in order to maintain the capability of the transistor, such as the voltage capacity between the source region and the drain region during operation, at a desired level. However, when the impurity concentration of the source region and the drain region is low, the resistance of the source region and the drain region increases. This affects the operating speed of the transistor.